drivers/mmc/host/bfin_sdh.c

   1 /*
   2  * bfin_sdh.c - Analog Devices Blackfin SDH Controller
   3  *
   4  * Copyright (C) 2007-2009 Analog Device Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #define DRIVER_NAME     "bfin-sdh"
  10
  11 #include <linux/module.h>
  12 #include <linux/init.h>
  13 #include <linux/ioport.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/mmc/host.h>
  19 #include <linux/proc_fs.h>
  20 #include <linux/gfp.h>
  21
  22 #include <asm/cacheflush.h>
  23 #include <asm/dma.h>
  24 #include <asm/portmux.h>
  25 #include <asm/bfin_sdh.h>
  26
  27 #if defined(CONFIG_BF51x)
  28 #define bfin_read_SDH_PWR_CTL           bfin_read_RSI_PWR_CTL
  29 #define bfin_write_SDH_PWR_CTL          bfin_write_RSI_PWR_CTL
  30 #define bfin_read_SDH_CLK_CTL           bfin_read_RSI_CLK_CTL
  31 #define bfin_write_SDH_CLK_CTL          bfin_write_RSI_CLK_CTL
  32 #define bfin_write_SDH_ARGUMENT         bfin_write_RSI_ARGUMENT
  33 #define bfin_write_SDH_COMMAND          bfin_write_RSI_COMMAND
  34 #define bfin_write_SDH_DATA_TIMER       bfin_write_RSI_DATA_TIMER
  35 #define bfin_read_SDH_RESPONSE0         bfin_read_RSI_RESPONSE0
  36 #define bfin_read_SDH_RESPONSE1         bfin_read_RSI_RESPONSE1
  37 #define bfin_read_SDH_RESPONSE2         bfin_read_RSI_RESPONSE2
  38 #define bfin_read_SDH_RESPONSE3         bfin_read_RSI_RESPONSE3
  39 #define bfin_write_SDH_DATA_LGTH        bfin_write_RSI_DATA_LGTH
  40 #define bfin_read_SDH_DATA_CTL          bfin_read_RSI_DATA_CTL
  41 #define bfin_write_SDH_DATA_CTL         bfin_write_RSI_DATA_CTL
  42 #define bfin_read_SDH_DATA_CNT          bfin_read_RSI_DATA_CNT
  43 #define bfin_write_SDH_STATUS_CLR       bfin_write_RSI_STATUS_CLR
  44 #define bfin_read_SDH_E_STATUS          bfin_read_RSI_E_STATUS
  45 #define bfin_write_SDH_E_STATUS         bfin_write_RSI_E_STATUS
  46 #define bfin_read_SDH_STATUS            bfin_read_RSI_STATUS
  47 #define bfin_write_SDH_MASK0            bfin_write_RSI_MASK0
  48 #define bfin_read_SDH_CFG               bfin_read_RSI_CFG
  49 #define bfin_write_SDH_CFG              bfin_write_RSI_CFG
  50 #endif
  51
  52 struct sdh_host {
  53         struct mmc_host         *mmc;
  54         spinlock_t              lock;
  55         struct resource         *res;
  56         void __iomem            *base;
  57         int                     irq;
  58         int                     stat_irq;
  59         int                     dma_ch;
  60         int                     dma_dir;
  61         struct dma_desc_array   *sg_cpu;
  62         dma_addr_t              sg_dma;
  63         int                     dma_len;
  64
  65         unsigned int            imask;
  66         unsigned int            power_mode;
  67         unsigned int            clk_div;
  68
  69         struct mmc_request      *mrq;
  70         struct mmc_command      *cmd;
  71         struct mmc_data         *data;
  72 };
  73
  74 static struct bfin_sd_host *get_sdh_data(struct platform_device *pdev)
  75 {
  76         return pdev->dev.platform_data;
  77 }
  78
  79 static void sdh_stop_clock(struct sdh_host *host)
  80 {
  81         bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() & ~CLK_E);
  82         SSYNC();
  83 }
  84
  85 static void sdh_enable_stat_irq(struct sdh_host *host, unsigned int mask)
  86 {
  87         unsigned long flags;
  88
  89         spin_lock_irqsave(&host->lock, flags);
  90         host->imask |= mask;
  91         bfin_write_SDH_MASK0(mask);
  92         SSYNC();
  93         spin_unlock_irqrestore(&host->lock, flags);
  94 }
  95
  96 static void sdh_disable_stat_irq(struct sdh_host *host, unsigned int mask)
  97 {
  98         unsigned long flags;
  99
 100         spin_lock_irqsave(&host->lock, flags);
 101         host->imask &= ~mask;
 102         bfin_write_SDH_MASK0(host->imask);
 103         SSYNC();
 104         spin_unlock_irqrestore(&host->lock, flags);
 105 }
 106
 107 static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data)
 108 {
 109         unsigned int length;
 110         unsigned int data_ctl;
 111         unsigned int dma_cfg;
 112         unsigned int cycle_ns, timeout;
 113
 114         dev_dbg(mmc_dev(host->mmc), "%s enter flags: 0x%x\n", __func__, data->flags);
 115         host->data = data;
 116         data_ctl = 0;
 117         dma_cfg = 0;
 118
 119         length = data->blksz * data->blocks;
 120         bfin_write_SDH_DATA_LGTH(length);
 121
 122         if (data->flags & MMC_DATA_STREAM)
 123                 data_ctl |= DTX_MODE;
 124
 125         if (data->flags & MMC_DATA_READ)
 126                 data_ctl |= DTX_DIR;
 127         /* Only supports power-of-2 block size */
 128         if (data->blksz & (data->blksz - 1))
 129                 return -EINVAL;
 130         data_ctl |= ((ffs(data->blksz) - 1) << 4);
 131
 132         bfin_write_SDH_DATA_CTL(data_ctl);
 133         /* the time of a host clock period in ns */
 134         cycle_ns = 1000000000 / (get_sclk() / (2 * (host->clk_div + 1)));
 135         timeout = data->timeout_ns / cycle_ns;
 136         timeout += data->timeout_clks;
 137         bfin_write_SDH_DATA_TIMER(timeout);
 138         SSYNC();
 139
 140         if (data->flags & MMC_DATA_READ) {
 141                 host->dma_dir = DMA_FROM_DEVICE;
 142                 dma_cfg |= WNR;
 143         } else
 144                 host->dma_dir = DMA_TO_DEVICE;
 145
 146         sdh_enable_stat_irq(host, (DAT_CRC_FAIL | DAT_TIME_OUT | DAT_END));
 147         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma_dir);
 148 #if defined(CONFIG_BF54x)
 149         dma_cfg |= DMAFLOW_ARRAY | NDSIZE_5 | RESTART | WDSIZE_32 | DMAEN;
 150         {
 151                 struct scatterlist *sg;
 152                 int i;
 153                 for_each_sg(data->sg, sg, host->dma_len, i) {
 154                         host->sg_cpu[i].start_addr = sg_dma_address(sg);
 155                         host->sg_cpu[i].cfg = dma_cfg;
 156                         host->sg_cpu[i].x_count = sg_dma_len(sg) / 4;
 157                         host->sg_cpu[i].x_modify = 4;
 158                         dev_dbg(mmc_dev(host->mmc), "%d: start_addr:0x%lx, "
 159                                 "cfg:0x%x, x_count:0x%x, x_modify:0x%x\n",
 160                                 i, host->sg_cpu[i].start_addr,
 161                                 host->sg_cpu[i].cfg, host->sg_cpu[i].x_count,
 162                                 host->sg_cpu[i].x_modify);
 163                 }
 164         }
 165         flush_dcache_range((unsigned int)host->sg_cpu,
 166                 (unsigned int)host->sg_cpu +
 167                         host->dma_len * sizeof(struct dma_desc_array));
 168         /* Set the last descriptor to stop mode */
 169         host->sg_cpu[host->dma_len - 1].cfg &= ~(DMAFLOW | NDSIZE);
 170         host->sg_cpu[host->dma_len - 1].cfg |= DI_EN;
 171
 172         set_dma_curr_desc_addr(host->dma_ch, (unsigned long *)host->sg_dma);
 173         set_dma_x_count(host->dma_ch, 0);
 174         set_dma_x_modify(host->dma_ch, 0);
 175         set_dma_config(host->dma_ch, dma_cfg);
 176 #elif defined(CONFIG_BF51x)
 177         /* RSI DMA doesn't work in array mode */
 178         dma_cfg |= WDSIZE_32 | DMAEN;
 179         set_dma_start_addr(host->dma_ch, sg_dma_address(&data->sg[0]));
 180         set_dma_x_count(host->dma_ch, length / 4);
 181         set_dma_x_modify(host->dma_ch, 4);
 182         set_dma_config(host->dma_ch, dma_cfg);
 183 #endif
 184         bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
 185
 186         SSYNC();
 187
 188         dev_dbg(mmc_dev(host->mmc), "%s exit\n", __func__);
 189         return 0;
 190 }
 191
 192 static void sdh_start_cmd(struct sdh_host *host, struct mmc_command *cmd)
 193 {
 194         unsigned int sdh_cmd;
 195         unsigned int stat_mask;
 196
 197         dev_dbg(mmc_dev(host->mmc), "%s enter cmd: 0x%p\n", __func__, cmd);
 198         WARN_ON(host->cmd != NULL);
 199         host->cmd = cmd;
 200
 201         sdh_cmd = 0;
 202         stat_mask = 0;
 203
 204         sdh_cmd |= cmd->opcode;
 205
 206         if (cmd->flags & MMC_RSP_PRESENT) {
 207                 sdh_cmd |= CMD_RSP;
 208                 stat_mask |= CMD_RESP_END;
 209         } else {
 210                 stat_mask |= CMD_SENT;
 211         }
 212
 213         if (cmd->flags & MMC_RSP_136)
 214                 sdh_cmd |= CMD_L_RSP;
 215
 216         stat_mask |= CMD_CRC_FAIL | CMD_TIME_OUT;
 217
 218         sdh_enable_stat_irq(host, stat_mask);
 219
 220         bfin_write_SDH_ARGUMENT(cmd->arg);
 221         bfin_write_SDH_COMMAND(sdh_cmd | CMD_E);
 222         bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() | CLK_E);
 223         SSYNC();
 224 }
 225
 226 static void sdh_finish_request(struct sdh_host *host, struct mmc_request *mrq)
 227 {
 228         dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
 229         host->mrq = NULL;
 230         host->cmd = NULL;
 231         host->data = NULL;
 232         mmc_request_done(host->mmc, mrq);
 233 }
 234
 235 static int sdh_cmd_done(struct sdh_host *host, unsigned int stat)
 236 {
 237         struct mmc_command *cmd = host->cmd;
 238         int ret = 0;
 239
 240         dev_dbg(mmc_dev(host->mmc), "%s enter cmd: %p\n", __func__, cmd);
 241         if (!cmd)
 242                 return 0;
 243
 244         host->cmd = NULL;
 245
 246         if (cmd->flags & MMC_RSP_PRESENT) {
 247                 cmd->resp[0] = bfin_read_SDH_RESPONSE0();
 248                 if (cmd->flags & MMC_RSP_136) {
 249                         cmd->resp[1] = bfin_read_SDH_RESPONSE1();
 250                         cmd->resp[2] = bfin_read_SDH_RESPONSE2();
 251                         cmd->resp[3] = bfin_read_SDH_RESPONSE3();
 252                 }
 253         }
 254         if (stat & CMD_TIME_OUT)
 255                 cmd->error = -ETIMEDOUT;
 256         else if (stat & CMD_CRC_FAIL && cmd->flags & MMC_RSP_CRC)
 257                 cmd->error = -EILSEQ;
 258
 259         sdh_disable_stat_irq(host, (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL));
 260
 261         if (host->data && !cmd->error) {
 262                 if (host->data->flags & MMC_DATA_WRITE) {
 263                         ret = sdh_setup_data(host, host->data);
 264                         if (ret)
 265                                 return 0;
 266                 }
 267
 268                 sdh_enable_stat_irq(host, DAT_END | RX_OVERRUN | TX_UNDERRUN | DAT_TIME_OUT);
 269         } else
 270                 sdh_finish_request(host, host->mrq);
 271
 272         return 1;
 273 }
 274
 275 static int sdh_data_done(struct sdh_host *host, unsigned int stat)
 276 {
 277         struct mmc_data *data = host->data;
 278
 279         dev_dbg(mmc_dev(host->mmc), "%s enter stat: 0x%x\n", __func__, stat);
 280         if (!data)
 281                 return 0;
 282
 283         disable_dma(host->dma_ch);
 284         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 285                      host->dma_dir);
 286
 287         if (stat & DAT_TIME_OUT)
 288                 data->error = -ETIMEDOUT;
 289         else if (stat & DAT_CRC_FAIL)
 290                 data->error = -EILSEQ;
 291         else if (stat & (RX_OVERRUN | TX_UNDERRUN))
 292                 data->error = -EIO;
 293
 294         if (!data->error)
 295                 data->bytes_xfered = data->blocks * data->blksz;
 296         else
 297                 data->bytes_xfered = 0;
 298
 299         sdh_disable_stat_irq(host, DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN);
 300         bfin_write_SDH_STATUS_CLR(DAT_END_STAT | DAT_TIMEOUT_STAT | \
 301                         DAT_CRC_FAIL_STAT | DAT_BLK_END_STAT | RX_OVERRUN | TX_UNDERRUN);
 302         bfin_write_SDH_DATA_CTL(0);
 303         SSYNC();
 304
 305         host->data = NULL;
 306         if (host->mrq->stop) {
 307                 sdh_stop_clock(host);
 308                 sdh_start_cmd(host, host->mrq->stop);
 309         } else {
 310                 sdh_finish_request(host, host->mrq);
 311         }
 312
 313         return 1;
 314 }
 315
 316 static void sdh_request(struct mmc_host *mmc, struct mmc_request *mrq)
 317 {
 318         struct sdh_host *host = mmc_priv(mmc);
 319         int ret = 0;
 320
 321         dev_dbg(mmc_dev(host->mmc), "%s enter, mrp:%p, cmd:%p\n", __func__, mrq, mrq->cmd);
 322         WARN_ON(host->mrq != NULL);
 323
 324         host->mrq = mrq;
 325         host->data = mrq->data;
 326
 327         if (mrq->data && mrq->data->flags & MMC_DATA_READ) {
 328                 ret = sdh_setup_data(host, mrq->data);
 329                 if (ret)
 330                         return;
 331         }
 332
 333         sdh_start_cmd(host, mrq->cmd);
 334 }
 335
 336 static void sdh_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 337 {
 338         struct sdh_host *host;
 339         unsigned long flags;
 340         u16 clk_ctl = 0;
 341         u16 pwr_ctl = 0;
 342         u16 cfg;
 343         host = mmc_priv(mmc);
 344
 345         spin_lock_irqsave(&host->lock, flags);
 346         if (ios->clock) {
 347                 unsigned long  sys_clk, ios_clk;
 348                 unsigned char clk_div;
 349                 ios_clk = 2 * ios->clock;
 350                 sys_clk = get_sclk();
 351                 clk_div = sys_clk / ios_clk;
 352                 if (sys_clk % ios_clk == 0)
 353                         clk_div -= 1;
 354                 clk_div = min_t(unsigned char, clk_div, 0xFF);
 355                 clk_ctl |= clk_div;
 356                 clk_ctl |= CLK_E;
 357                 host->clk_div = clk_div;
 358         } else
 359                 sdh_stop_clock(host);
 360
 361         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 362 #ifdef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
 363                 pwr_ctl |= ROD_CTL;
 364 #else
 365                 pwr_ctl |= SD_CMD_OD | ROD_CTL;
 366 #endif
 367
 368         if (ios->bus_width == MMC_BUS_WIDTH_4) {
 369                 cfg = bfin_read_SDH_CFG();
 370                 cfg &= ~PD_SDDAT3;
 371                 cfg |= PUP_SDDAT3;
 372                 /* Enable 4 bit SDIO */
 373                 cfg |= (SD4E | MWE);
 374                 bfin_write_SDH_CFG(cfg);
 375                 clk_ctl |= WIDE_BUS;
 376         } else {
 377                 cfg = bfin_read_SDH_CFG();
 378                 cfg |= MWE;
 379                 bfin_write_SDH_CFG(cfg);
 380         }
 381
 382         bfin_write_SDH_CLK_CTL(clk_ctl);
 383
 384         host->power_mode = ios->power_mode;
 385         if (ios->power_mode == MMC_POWER_ON)
 386                 pwr_ctl |= PWR_ON;
 387
 388         bfin_write_SDH_PWR_CTL(pwr_ctl);
 389         SSYNC();
 390
 391         spin_unlock_irqrestore(&host->lock, flags);
 392
 393         dev_dbg(mmc_dev(host->mmc), "SDH: clk_div = 0x%x actual clock:%ld expected clock:%d\n",
 394                 host->clk_div,
 395                 host->clk_div ? get_sclk() / (2 * (host->clk_div + 1)) : 0,
 396                 ios->clock);
 397 }
 398
 399 static const struct mmc_host_ops sdh_ops = {
 400         .request        = sdh_request,
 401         .set_ios        = sdh_set_ios,
 402 };
 403
 404 static irqreturn_t sdh_dma_irq(int irq, void *devid)
 405 {
 406         struct sdh_host *host = devid;
 407
 408         dev_dbg(mmc_dev(host->mmc), "%s enter, irq_stat: 0x%04x\n", __func__,
 409                 get_dma_curr_irqstat(host->dma_ch));
 410         clear_dma_irqstat(host->dma_ch);
 411         SSYNC();
 412
 413         return IRQ_HANDLED;
 414 }
 415
 416 static irqreturn_t sdh_stat_irq(int irq, void *devid)
 417 {
 418         struct sdh_host *host = devid;
 419         unsigned int status;
 420         int handled = 0;
 421
 422         dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
 423         status = bfin_read_SDH_E_STATUS();
 424         if (status & SD_CARD_DET) {
 425                 mmc_detect_change(host->mmc, 0);
 426                 bfin_write_SDH_E_STATUS(SD_CARD_DET);
 427         }
 428         status = bfin_read_SDH_STATUS();
 429         if (status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL)) {
 430                 handled |= sdh_cmd_done(host, status);
 431                 bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT | \
 432                                 CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
 433                 SSYNC();
 434         }
 435
 436         status = bfin_read_SDH_STATUS();
 437         if (status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN))
 438                 handled |= sdh_data_done(host, status);
 439
 440         dev_dbg(mmc_dev(host->mmc), "%s exit\n\n", __func__);
 441
 442         return IRQ_RETVAL(handled);
 443 }
 444
 445 static int __devinit sdh_probe(struct platform_device *pdev)
 446 {
 447         struct mmc_host *mmc;
 448         struct sdh_host *host;
 449         struct bfin_sd_host *drv_data = get_sdh_data(pdev);
 450         int ret;
 451
 452         if (!drv_data) {
 453                 dev_err(&pdev->dev, "missing platform driver data\n");
 454                 ret = -EINVAL;
 455                 goto out;
 456         }
 457
 458         mmc = mmc_alloc_host(sizeof(struct sdh_host), &pdev->dev);
 459         if (!mmc) {
 460                 ret = -ENOMEM;
 461                 goto out;
 462         }
 463
 464         mmc->ops = &sdh_ops;
 465         mmc->max_segs = 32;
 466         mmc->max_seg_size = 1 << 16;
 467         mmc->max_blk_size = 1 << 11;
 468         mmc->max_blk_count = 1 << 11;
 469         mmc->max_req_size = PAGE_SIZE;
 470         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 471         mmc->f_max = get_sclk();
 472         mmc->f_min = mmc->f_max >> 9;
 473         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NEEDS_POLL;
 474         host = mmc_priv(mmc);
 475         host->mmc = mmc;
 476
 477         spin_lock_init(&host->lock);
 478         host->irq = drv_data->irq_int0;
 479         host->dma_ch = drv_data->dma_chan;
 480
 481         ret = request_dma(host->dma_ch, DRIVER_NAME "DMA");
 482         if (ret) {
 483                 dev_err(&pdev->dev, "unable to request DMA channel\n");
 484                 goto out1;
 485         }
 486
 487         ret = set_dma_callback(host->dma_ch, sdh_dma_irq, host);
 488         if (ret) {
 489                 dev_err(&pdev->dev, "unable to request DMA irq\n");
 490                 goto out2;
 491         }
 492
 493         host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
 494         if (host->sg_cpu == NULL) {
 495                 ret = -ENOMEM;
 496                 goto out2;
 497         }
 498
 499         platform_set_drvdata(pdev, mmc);
 500         mmc_add_host(mmc);
 501
 502         ret = request_irq(host->irq, sdh_stat_irq, 0, "SDH Status IRQ", host);
 503         if (ret) {
 504                 dev_err(&pdev->dev, "unable to request status irq\n");
 505                 goto out3;
 506         }
 507
 508         ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
 509         if (ret) {
 510                 dev_err(&pdev->dev, "unable to request peripheral pins\n");
 511                 goto out4;
 512         }
 513 #if defined(CONFIG_BF54x)
 514         /* Secure Digital Host shares DMA with Nand controller */
 515         bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
 516 #endif
 517
 518         bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
 519         SSYNC();
 520
 521         /* Disable card inserting detection pin. set MMC_CAP_NEES_POLL, and
 522          * mmc stack will do the detection.
 523          */
 524         bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
 525         SSYNC();
 526
 527         return 0;
 528
 529 out4:
 530         free_irq(host->irq, host);
 531 out3:
 532         mmc_remove_host(mmc);
 533         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
 534 out2:
 535         free_dma(host->dma_ch);
 536 out1:
 537         mmc_free_host(mmc);
 538  out:
 539         return ret;
 540 }
 541
 542 static int __devexit sdh_remove(struct platform_device *pdev)
 543 {
 544         struct mmc_host *mmc = platform_get_drvdata(pdev);
 545
 546         platform_set_drvdata(pdev, NULL);
 547
 548         if (mmc) {
 549                 struct sdh_host *host = mmc_priv(mmc);
 550
 551                 mmc_remove_host(mmc);
 552
 553                 sdh_stop_clock(host);
 554                 free_irq(host->irq, host);
 555                 free_dma(host->dma_ch);
 556                 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
 557
 558                 mmc_free_host(mmc);
 559         }
 560
 561         return 0;
 562 }
 563
 564 #ifdef CONFIG_PM
 565 static int sdh_suspend(struct platform_device *dev, pm_message_t state)
 566 {
 567         struct mmc_host *mmc = platform_get_drvdata(dev);
 568         struct bfin_sd_host *drv_data = get_sdh_data(dev);
 569         int ret = 0;
 570
 571         if (mmc)
 572                 ret = mmc_suspend_host(mmc);
 573
 574         bfin_write_SDH_PWR_CTL(bfin_read_SDH_PWR_CTL() & ~PWR_ON);
 575         peripheral_free_list(drv_data->pin_req);
 576
 577         return ret;
 578 }
 579
 580 static int sdh_resume(struct platform_device *dev)
 581 {
 582         struct mmc_host *mmc = platform_get_drvdata(dev);
 583         struct bfin_sd_host *drv_data = get_sdh_data(dev);
 584         int ret = 0;
 585
 586         ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
 587         if (ret) {
 588                 dev_err(&dev->dev, "unable to request peripheral pins\n");
 589                 return ret;
 590         }
 591
 592         bfin_write_SDH_PWR_CTL(bfin_read_SDH_PWR_CTL() | PWR_ON);
 593 #if defined(CONFIG_BF54x)
 594         /* Secure Digital Host shares DMA with Nand controller */
 595         bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
 596 #endif
 597         bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
 598         SSYNC();
 599
 600         bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
 601         SSYNC();
 602
 603         if (mmc)
 604                 ret = mmc_resume_host(mmc);
 605
 606         return ret;
 607 }
 608 #else
 609 # define sdh_suspend NULL
 610 # define sdh_resume  NULL
 611 #endif
 612
 613 static struct platform_driver sdh_driver = {
 614         .probe   = sdh_probe,
 615         .remove  = __devexit_p(sdh_remove),
 616         .suspend = sdh_suspend,
 617         .resume  = sdh_resume,
 618         .driver  = {
 619                 .name = DRIVER_NAME,
 620         },
 621 };
 622
 623 module_platform_driver(sdh_driver);
 624
 625 MODULE_DESCRIPTION("Blackfin Secure Digital Host Driver");
 626 MODULE_AUTHOR("Cliff Cai, Roy Huang");
 627 MODULE_LICENSE("GPL");